With the advent of less expensive semiconductor memory, modern computer and microcomputer systems have been able to use bit-mapped video displays for the output of data from the system. As is well known, a bit-mapped video display requires a memory bit-mapped which can store at least one binary digit (bit) of information for each picture element (pixel) of the display device. Additional bits stored for each pixel provide the capability of the system to render complex images on the video display, such as multi-color images, and background and foreground images, such as a graphics background with textual information overlaid thereupon. The use of bit-mapped memory for storing image information also allows for data processing operations to easily generate and modify the stored image.
Modern video display devices are often of the raster-scan type, where an electron gun traces horizontal lines across the display screen in order to generate the desired image. In order for a raster scan image to continue to be displayed on the video screen, the image must be refreshed during periodic intervals. A common refresh interval for the cathode ray tube video display devices is 1/60 of a second, since the refresh operation carried out during that length interval is not noticable to the human user of the system. However, as the number of pixels displayed on a screen increases, in order to increase the resolution of the displayed image, more and more bits of information must be accessed from the bit-mapped memory during the refresh interval. If the bit-mapped memory has but a single input and output port, the percentage of time during which the data processing unit can access the bit-mapped memory varies inversely with the number of bits per pixel for the display so long as the refresh interval remains constant. In addition, the speed of the memory must increase with the number of bits per pixel, since more bits must be output during a fixed period of time.
Multiport random access memories have been developed which provide for high-speed output of data to the video display and also for increased accessibility of the memory contents to the data processing device. The multiport memories accomplish this by having a first port for random access and update of the memory by the data processing unit of the computer system and a second port for serial output of the memory contents to the video display independent from arid asynchronous with the first port, thereby allowing access to the memory contents during output of data to the video display terminal. Examples of multiport random access memories are described in U.S. Pat. No. 4,562,435 (issued Dec. 31, 1985), U.S. Pat. No. 4,639,890 (issued Jan. 27, 1987), and U.S. Pat. No. 4,636,986 (issued Jan. 13, 1987), all assigned to Texas Instruments Incorporated.
The multiport random access memory described in said U.S. Pat. No. 4,636,986 has four random access input/output terminals, and four serial access input/output terminals, so that the single memory device appears to have four memory arrays. This allows a single random access to read or write four data bits simultaneously, with a single address value, and also allows a by-four serial output for purposes of data communication to the video display. In a monochrome display system, for example, an external parallel-to-serial register can then receive the by-four serial output bits, and shift them one at a time to the video display at the display refresh rate. The buffering provided by the external parallel-to-serial register allows the memory serial register to shift at a rate 1/N of the rate of the video display (N being the number of serial outputs received by the parallel-to-serial register), further reducing the speed requirements of the semiconductor memory.
Other uses of the by-four organization provide for enhanced image display capabilities. For example, the by-four organization is useful in multi-color displays, since the four bits associated with each address can be associated with a common picture element ("pixel") of the display device. Such a configuration provides for the storage of a four bit binary code representative of color for each corresponding pixel of the video display. Another use of the four bits is to assign one of the bits or representing text, and the other three bits for representing color for a graphical background. The by-four memory thus facilitates the overlaying of a text message on a graphics image.
Referring to FIG. 10, a double-buffered display memory is shown. Such a system provides for the storage of updated display information into one of the frame buffers while the other buffer is providing its contents to the display device. A central processing unit 250 has its data output connected to a demultiplexer 252, shown schematically as providing data to memory plane groups 254A and 254B, each of which have N bit planes of bit-mapped data. Memory plane groups 254A and 254B provide data output to multiplexer 256, which provides an output to display 258. Control signals SEL and SEL.sub.--, the logical complement of one another, control the selection of demultiplexer 252 and multiplexer 256, respectively, so that memory plane group 254A is selected for input through demultiplexer 252 during such time as memory plane group 254B is selected for output through multiplexer 256 (and vice versa). In operation, one of memory plane groups 254 is providing display output to display 258 during such time as CPU 250 is providing input to the other memory plane group 254. After the display is completed, lines SEL and SEL.sub.-- toggle to the opposite data state, so that the opposite memory plane groups 254 receive data from CPU 250 and present data to display 258.
In such applications, it is often useful to clear, or write a particular data state, into a large number of memory locations in one of the planes. In the configuration where one of the bit planes carries the textual information. For example, it is useful to be able to clear the textual message without disturbing the other bit planes associated with the same pixels. If random accesses to each of the memory locations is required to write the desired "clear" data into each of the accessed locations, such an operation may take a large number of memory cycles, during which other operations on the display memory are precluded.
In the double-buffered system of FIG. 10, it is common practice to clear the contents of selected ones within the memory plane groups 254 to which data is to be provided, prior to the application of the updated data thereto. This allows CPU 250 to provide to the memory plane group 254 only the data required to draw the displayed image, as the background color information may be left undisturbed in the unselected ones of the memory planes. If random accesses of each memory location in a memory plane is required for the clearing operation, however, the time required for clearing subtracts from the time available for image drawing, as the clearing and drawing operation in the one of memory plane groups 254 selected to receive data is fixed by the time required for the other memory plane group to present its data to display 258.
It is therefore an object of this invention to provide a dual-port memory device having a selectable mode in which a large number of memory cells may be forced to a preselected data state in a single write cycle.
It is another object to provide such a dual-port memory with such mode, where said multiple memory cells consists of an entire row memory cells.
It is another object of this invention to provide such a dual-port memory, where the memory is organized in such a manner that it communicates with a plurality of parallel inputs, and where such a row write operation may be inhibited for memory cells associated with selected ones of said inputs during the write cycle.
It is therefore yet another object of this invention to provide such a dual-port memory having such a mode, and which further includes a data register containing the data states to be forced into the memory cells in the selected row during the given write cycle.
It is yet another object of this invention to provide such capability by a single capacitor and transistor associated with multiple columns in the memory device, thereby minimizing the silicon area required for the incorporation of the invention.
Other objects and advantages of the instant invention will become apparent to those of ordinary skill in the art having reference to the following specification, in combination with the drawings.